Vishay-Intertech-SI5442DU-T1-GE3
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Si5442DU
Vishay Siliconix
N-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
•
TrenchFET
®
Power MOSFET
V
DS
(V)
R
DS(on)
(
) Max.
0.0100 at V
GS
= 4.5 V
0.0115 at V
GS
= 2.5 V
0.0135 at V
GS
= 1.8 V
Q
g
(Typ.)
I
D
(A)
a
25
Thermally Enhanced PowerPAK
®
ChipFET
®
Package
– Small Footprint Area
– Low On-Resistance
– Thin 0.8 mm Profile
100% R
g
Tested
25
20
16.6 nC
25
•
•
Material categorization: For definitions of compliance
PowerPAK ChipFET Sin
g
le
1
2
APPLICATIONS
•
•
•
•
Load Switch, PA Switch, and for Portable Applications
Point-of-Load
D
3
D
D
4
DC/DC Converters
Power Management
D
D
8
G
D
D
7
S
6
S
Marking Code
5
AQ
XXX
Lot Tracea
b
ility
and Date Code
Bottom
V
ie
w
G
Part # Code
Orderin
g
Information:
Si5442DU-T1-GE3 (Lead (P
b
)-free and Halogen-free)
S
N
-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS
(T =
25 °C, unless otherwise noted)
A
Limit
20
Parameter
Symbol
Unit
V
DS
Drain-Source Voltage
Gate-Source Voltage
V
V
GS
8
25
a
T
T
C
= 25 °C
C
= 70 °C
25
a
Continuous Drain Current (T
J
= 150 °C)
I
D
12.4
b, c
9.9
b, c
60
25
a
2.6
b, c
31
T
A
= 25 °C
T
A
= 70 °C
A
I
DM
I
S
Pulsed Drain Current (t = 300 µs)
T
C
= 25 °C
T
A
= 25 °C
Continuous Source-Drain Diode Current
T
C
= 25 °C
T
C
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
20
P
D
Maximum Power Dissipation
W
3.1
b, c
2
b, c
T
J
, T
stg
– 55 to 150
260
Operating Junction and Storage
T
e
mperature Range
Soldering Recommendations (Peak
T
e
mperature)
d, e
°C
THERMAL RESISTANCE RATINGS
Parameter
Typical
Maximum
Symbol
Unit
Maximum Junction-to-Ambient
b, f
Maximum Junction-to-Case (Drain)
t
5 s
Steady State
34
40
R
thJA
R
thJC
°C/W
3
4
Notes:
a. Package limited.
b. Surface mounted on 1″ x 1″ FR4 board.
c. t = 5 s.
d. See solder profile (
www.vishay.com/doc?73257
). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum
under steady state conditions is 90 °C/W.
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
1
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5442DU
Vishay Siliconix
SPECIFICATIONS
(T =
25 °C, unless otherwise noted)
J
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
V
GS
= 0
V
,
I
D
= 250 µA
I
D
= 250 µA
Drain-Source Breakdown Voltage
20
V
V
DS
T
e
mperature Coefficient
21
– 3
mV/°C
V
GS(th)
T
e
mperature Coefficient
V
DS
= V
GS
, I
D
= 250 µA
V
Gate-Source Threshold Voltage
Gate-Source Leakage
0.4
20
0.9
100
1
I
GSS
V
DS
= 0
V
,
V
GS
=
8 V
nA
V
DS
= 20
V
,
V
GS
= 0 V
DS
= 20
V
,
V
GS
= 0
V
,
T
J
= 55 °C
V
DS
5
V
,
V
GS
= 4.5 V
V
GS
4.5
V
,
I
D
= 8 A
I
DSS
µA
A
Zero Gate Voltage Drain Current
On-State Drain Current
a
V
10
I
D(on)
0.0080
0.0090
0.0100
65
0.0100
0.0115
0.0135
Drain-Source On-State Resistance
a
R
DS(on)
V
GS
2.5
V
,
I
D
= 7 A
V
GS
1.8
V
,
I
D
= 4 A
Forward
T
r
ansconductance
a
g
fs
V
DS
= 10
V
,
I
D
= 8 A
S
Dynamic
b
C
iss
C
oss
C
rss
Input Capacitance
1700
280
115
29
V
DS
= 10
V
,
V
GS
= 0
V
, f = 1
M
Hz
Output Capacitance
pF
Reverse
T
r
ansfer Capacitance
V
DS
= 10
V
,
V
GS
= 8
V
,
I
D
= 15 A
45
25
T
o
tal Gate Charge
Q
g
16.6
1.9
2
nC
Q
gs
Q
gd
R
g
Gate-Source Charge
V
DS
= 10
V
,
V
GS
= 4.5
V
,
I
D
= 15 A
f = 1 MHz
Gate-Drain Charge
Gate Resistance
0.28
1.4
10
2.8
20
30
70
20
20
20
60
20
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
T
u
rn-on Delay Time
V
DD
= 10
V
,
R
L
= 1
Rise Time
15
I
D
10 A, V
GEN
= 4.5
V
,
R
g
= 1
T
u
rn-Off Delay Time
35
Fall Time
10
ns
T
u
rn-On Delay Time
10
V
DD
= 10
V
,
R
L
= 1
Rise Time
10
I
D
10 A, V
GEN
= 8
V
,
R
g
= 1
T
u
rn-Off Delay Time
30
Fall Time
10
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
25
60
1.2
40
20
A
I
S
= 10 A, V
GS
= 0 V
0.8
20
10
11
9
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
Q
rr
t
a
I
F
= 10 A, dI/dt = 100 A/µs, T
J
= 25 °C
ns
t
b
Notes:
a. Pulse test; pulse width
300 µs, duty cycle
2 %
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
60
50
40
30
20
10
0
20
16
12
8
V
GS
= 5 V thru 2 V
V
GS
= 1.5 V
T
C
= 25
°
C
4
T
C
= 125
°
C
V
GS
= 1 V
2.5
T
C
= – 55
°
C
0
0.0
0.5
1.0
1.5
2.0
3.0
0.0
0.3
0.6
0.9
1.2
1.5
V
GS
– Gate-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.014
0.012
0.010
0.008
0.006
0.004
2500
2000
1500
1000
500
C
iss
V
GS
= 1.8 V
V
GS
= 2.5 V
V
GS
= 4.5 V
C
oss
C
rss
0
0
10
20
30
40
50
60
0
4
8
12
16
20
V
DS
– Drain-to-Source Voltage (V)
I
D
– Drain Current (A)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
1.6
1.4
1.2
1.0
0.8
0.6
8
V
GS
= 4.5 V, 2.5 V
I
D
= 8 A
I
D
= 15 A
V
DS
= 10 V
6
4
2
0
V
GS
= 1.8 V
V
DS
= 16 V
V
DS
= 5 V
– 50
– 25
0
25
50
75
100 125 150
0
5
10
15
20
25
30
Q
g
– Total Gate Charge (nC)
T
J
– Junction Temperature (
°
C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
3
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
0.025
0.020
0.015
0.010
0.005
0.000
100
10
1
I
D
= 8 A
T
J
= 150
°
C
T
J
= 125
°
C
T
J
= 25
°
C
T
J
= 25
°
C
0.1
0.0
0.2
0.4
0.6
0.8
1.0
0.0
1.0
2.0
3.0
4.0
5.0
V
SD
– Source-to-Drain Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
50
40
30
20
10
I
D
= 250 μA
0
– 50
– 25
0
25
50
75
100 125 150
0.001 0.01
0.1
1
10
100
1000
Time (s)
T
J
– Temperature (
°
C)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
10
1
Limited by R
DS(on)
*
100 μs
1 ms
10 ms
100 ms
1 s
10 s
0.1
T
A
= 25
°
C
DC
BVDSS Limited
0.01
0.1
1
10
100
V
DS
– Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is specified
Safe Operating Area, Junction-to-Ambient
4
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
35
30
25
20
15
10
5
50
40
30
20
10
0
Package Limited
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
– Case Temperature (
°
C)
T
C
– Case
T
e
mperat
u
re (°C)
Current Derating*
Power Derating
* The power dissipation P
D
is based on T
J(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
5
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Si5442DU
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
1
D
u
ty Cycle = 0.5
0.2
N
otes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
1. D
u
ty Cycle, D =
0.02
2
2. Per Unit Base = R
= 90 °C/
W
thJA
(t)
3. T
– T
= P
JM
Z
A
DM thJA
Single P
u
lse
4. S
u
rface Mo
u
nted
0.01
-4
-3
-2
-1
10
10
10
10
1
10
100
1000
S
qu
are
W
a
v
e P
u
lse D
u
ration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
D
u
ty Cycle = 0.5
0.2
0.1
0.05
0.02
Single P
u
lse
0.1
10
-4
-3
-2
-1
10
10
S
qu
are
W
a
v
e P
u
lse D
u
ration (s)
10
1
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
6
Document Number: 63233
S13-2149-Rev. B, 14-Oct-13
For technical questions, contact:
pmostechsupport@visha
y
.
com
This document is subject to change without notice.
Package Information
Vishay Siliconix
PowerPAK
®
ChipFET
®
Case Outline
D
(8)
(7)
(6)
(5)
Pin #1
indicator
(1)
(2)
(3)
(4)
S
ide view of
s
ingle
S
ide view of dual
Z
e
b
D2
D2
D1
K
Detail Z
H
L
D(1) D(2)
D(3)
G
(4)
S
I(1)
G
I(2)
S
2(3)
G
2(4)
K1
E1
E3
D3
D(8)
D(7) D(6)
S
(5)
D1(8) D1(7)
D2(6) D2(5)
K3
Back
s
ide view of
s
ingle pad
Back
s
ide view of dual pad
MILLIMETERS
INCHES
NOM.
0.030
–
DIM.
MIN.
0.70
0
NOM.
0.75
–
MAX.
0.85
0.05
0.35
0.25
3.08
2.00
1.32
0.30
1.98
1.63
1.17
0.55
MIN.
0.028
0
MAX.
0.033
0.002
0.014
0.010
0.121
0.079
0.052
0.012
0.078
0.064
0.046
0.022
A
A1
b
0.25
0.15
2.92
1.75
1.07
0.20
1.82
1.38
0.92
0.45
0.30
0.20
3.00
1.87
1.20
0.25
1.90
1.50
1.05
0.50
0.65 BSC
0.20
–
0.010
0.006
0.115
0.069
0.042
0.008
0.072
0.054
0.036
0.018
0.012
0.008
0.118
0.074
0.047
0.010
0.075
0.059
0.041
0.020
0.026 BSC
0.008
–
C
D
D1
D2
D3
E
E1
E2
E3
e
H
0.15
0.25
0.30
0.20
0.20
0.30
0.25
0.006
0.010
0.012
0.008
0.008
0.012
0.010
K
–
–
K1
K2
K3
L
–
–
–
–
–
–
–
–
–
–
–
–
0.35
0.40
0.014
0.016
C14-0630-Rev. E, 21-Jul-14
DWG: 5940
Note
Millimeters will govern
•
Revision: 21-Jul-14
Document Number: 73203
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR Power
P
A
K
®
ChipFET
®
Single
0.225
(0.009)
0.350
(0.014)
0.650
(0.026)
0.200
(0.00
8
)
0.300
(0.012)
0.300
(0.012)
0.100
(0.004)
0.250
(0.010)
0.500
(0.020)
0.350
(0.014)
0.350
(0.014)
1.
8
70
0.305
(0.074)
(0.012)
2.575
(0.101)
Recommended Minim
u
m Pads
Dimensions in mm/(Inches)
Return to Index
Document Number: 69948
Revision: 21-Jan-08
9
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product.
To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications.
Such statements are not binding
statements about the suitability of products for a particular application.
It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts.
Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay.
Product names and markings noted herein may be trademarks of their respective owners.
© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
1
