Vishay-Intertech-SI5504BDC-T1-GE3
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Si5504BDC
Vishay Siliconix
N- and P-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
• TrenchFET
®
Power MOSFETs
V
DS
(V)
R
DS(on)
(
)
I
D
(A) Q
g
(TYP.)
• Material categorization:
For definitions of compliance please see
0.065 at V
GS
= 10 V
0.100 at V
GS
= 4.5 V
0.140 at V
GS
= -10 V
0.235 at V
GS
= -4.5 V
4
a
N-Channel
P-Channel
30
2 nC
4
a
-3.7
-30
2.2 nC
-2.8
APPLICATIONS
Available
• DC/DC for portable applications
• Load switch
1206-8 ChipFET
®
Dual
D
1
8
D
1
D
2
6
7
D
2
5
S
2
D
1
1
S
1
2
G
1
3
S
2
G
2
4
G
2
G
1
Top View
Bottom View
Marking Code:
EF
S
1
D
2
Ordering Information:
Si5504BDC-T1-E3 (Lead (Pb)-free)
N-Channel MOSFET
P-Channel MOSFET
Si5504BDC-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
N-CHANNEL
P-CHANNEL
UNIT
Drain-Source Voltage
Gate-Source Voltage
V
DS
30
-30
V
V
GS
20
T
C
= 25 °C
T
C
= 85 °C
T
A
= 25 °C
T
A
= 85 °C
4
a
3.8
3.7
b,c
2.6
b,c
10
-3.7
-2.7
-2.5
b,c
-1.8
b,c
-10
Continuous Drain Current (T
J
= 150 °C)
I
D
A
Pulsed Drain Current
I
DM
I
S
T
C
= 25 °C
2.5
-2.5
-1.3
b,c
Source Drain Current Diode Current
T
A
= 25 °C
T
C
= 25 °C
1.3
b,c
3.12
2
1.5
b,c
0.8
b,c
3.1
T
C
= 85 °C
2
Maximum Power Dissipation
P
D
W
T
A
= 25 °C
T
A
= 85 °C
1.5
b,c
0.8
b,c
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
d,e
T
J
, T
stg
-55 to 150
260
°C
THERMAL RESISTANCE RATINGS
N-CHANNEL
P-CHANNEL
PARAMETER
SYMBOL
UNIT
TYP.
70
MAX.
TYP.
70
MAX.
85
Maximum Junction-to-Ambient
b,f
Maximum Junction-to-Foot (Drain)
t
5 s
R
thJA
R
thJF
85
40
°C/W
Steady State
33
33
40
Notes
a. Package
limited.
b. Surface
mounted on 1″ x 1″ FR4 board.
c. t
= 5 s.
d. See
reliability manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequade bottom side solder interconnection.
e. Rework
conditions: Manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum
under steady state conditions is 120 °C/W.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP. MAX. UNIT
Static
V
GS
= 0 V, I
D
= 250 μA
V
GS
= 0 V, I
D
= -250 μA
I
D
= 250 μA
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
30
–
–
–
Drain-Source Breakdown Voltage
V
DS
V
DS
/T
J
V
GS(th)
/T
J
V
GS(th)
V
-30
–
–
–
27
-30
-5
3.5
–
V
DS
Temperature Coefficient
GS(th)
Temperature Coefficient
I
D
= -250 μA
–
–
mV/°C
I
D
= 250 μA
I
D
= -250 μA
–
–
V
–
–
V
DS
= V
GS
, I
D
= 250 μA
1.5
3
Gate Threshold Voltage
Gate-Body Leakage
V
V
DS
= V
GS
, I
D
= -250 μA
V
DS
= 0 V, V
GS
20 V
V
DS
= 30 V, V
GS
= 0 V
-1.5
–
-3
100
-100
1
–
–
–
I
GSS
=
nA
–
–
–
V
DS
= -30 V, V
GS
= 0 V
V
DS
= 30 V, V
GS
= 0 V, T
J
= 85 °C
V
DS
= -30 V, V
GS
= 0 V, T
J
= 85 °C
V
DS
5 V, V
GS
= 10 V
–
–
-1
5
Zero Gate Voltage Drain Current
On-State Drain Current
b
I
DSS
I
D(on)
R
DS(on)
g
fs
μA
A
–
–
–
–
-5
–
10
-10
–
–
V
DS
-5 V, V
GS
= -10 V
–
–
V
GS
= 10 V, I
D
= 3.1 A
0.053 0.065
0.112 0.140
0.081 0.100
0.188 0.235
V
GS
= -10 V, I
D
= -2.1 A
V
GS
= 4.5 V, I
D
= 1 A
–
Drain-Source On-State Resistance
b
S
–
V
GS
= -4.5 V, I
D
= -0.43 A
V
DS
= 15 V, I
D
= 3.1 A
V
DS
= -15 V, I
D
= -2.1 A
–
–
5
–
–
Forward Transconductance
b
Dynamic
a
–
3.5
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
220
170
50
50
25
31
4.5
4.5
2
–
–
Input Capacitance
C
iss
C
oss
C
rss
N-Channel
DS
= 15 V, V
GS
= 0 V, f = 1 MHz
V
–
Output Capacitance
pF
–
P-Channel
DS
= -15 V, V
GS
= 0 V, f = 1 MHz
V
–
Reverse Transfer Capacitance
–
V
DS
= 15 V, V
GS
= 10 V, I
D
= 3.6 A
V
DS
= -15 V, V
GS
= -10 V, I
D
= -2.5 A
7
7
3
3.5
–
Total Gate Charge
Q
g
N-Channel
DS
= 15 V, V
GS
= 4.5 V, I
D
= 3.6 A
2.2
0.7
0.7
0.7
1
nC
V
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Q
gs
Q
gd
R
g
–
P-Channel
V
DS
= -15 V, V
GS
= -4.5 V, I
D
= -2.5 A
f = 1 MHz
–
–
3
–
13
–
Notes
a. Guaranteed
by design, not subject to production testing.
b. Pulse
test; pulse width
300 μs, duty cycle
2 %.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
2
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Dynamic
a
SYMBOL
TEST CONDITIONS
MIN.
TYP. MAX. UNIT
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
15
30
80
60
12
10
25
10
4
25
45
120
90
20
15
40
15
8
Turn-On Delay Time
Rise Time
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
N-Channel
DD
= 15 V, R
L
= 5.8
I
D
2.6 A, V
GEN
= 4.5 V, R
g
= 1
V
P-Channel
DD
= -15 V, R
L
= 7.5
I
D
-2 A, V
GEN
= -4.5 V, R
g
= 1
Turn-Off Delay Time
Fall Time
V
ns
Turn-On Delay Time
Rise Time
4
8
N-Channel
DD
= 15 V, R
L
= 5.8
I
D
2.6 A, V
GEN
= 10 V, R
g
= 1
V
12
10
10
10
5
20
15
15
15
10
10
P-Channel
DD
= -15 V, R
L
= 7.5
I
D
-2 A, V
GEN
= -10 V, R
g
= 1
Turn-Off Delay Time
V
Fall Time
5
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.5
-2.5
10
-10
1.2
-1.2
50
40
40
20
–
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
A
–
Pulse Diode Forward Current
a
Body Diode Voltage
–
I
S
= 2.6 A, V
GS
= 0 V
I
S
= -2 A, V
GS
= 0 V
0.8
-0.8
30
20
20
10
23
13
7
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
nC
N-Channel
I
F
= 2.6 A, dI/dt = 100 A/μs, T
J
= 25 °C
Q
rr
t
a
P-Channel
I
F
= -2 A, dI/dt = -100 A/μs, T
J
= 25 °C
P-Ch
–
ns
N-Ch
P-Ch
–
t
b
7
–
Notes
a. Guaranteed
by design, not subject to production testing.
b. Pulse
test; pulse width
300 μs, duty cycle
2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
3
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
20
16
12
8
5
4
3
2
1
0
V
GS
= 10 V thru 6 V
5 V
T
= 25 °C
C
4 V
3 V
T
= 125 °C
C
4
T
= – 55 °C
3.5 4.0
C
0
0.0
0.5
V
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
– Gate-to-Source Voltage (V)
GS
2.0
2.5
3.0
– Drain-to-Source Voltage (V)
V
DS
Output Characteristics
Transfer Characteristics
0.20
0.16
0.12
0.08
0.04
0.00
300
250
200
150
100
50
C
iss
V
GS
= 4.5 V
V
GS
= 10 V
C
oss
C
rss
0
0
5
10
– Drain Current (A)
15
20
0
5
10
15
20
25
30
I
D
V
DS
– Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
10
8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
V
D
= 10
V
,
4
.5 V
GS
= 3.1 A
V
DS
= 15
V
, I
=
3
.6 A
D
I
6
4
V
DS
= 24
V
, I
=
3
.6 A
D
2
0
0
1
2
3
4
5
– 50
– 25
0
25
50
75
100 125 150
Q
–
T
o
tal Gate Charge (nC)
T –
Junction
T
e
mperature (°C)
J
g
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 74483
S13-2463-Rev. C, 02-Dec-13
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
10
0.20
0.16
0.12
0.08
0.04
I
D
= 3.1 A
T
= 150 °C
J
125 °C
T
= 25 °C
J
25 °C
1
0.0
0
2
4
6
8
10
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
– Gate-to-Source Voltage (V)
V
SD
– Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
50
40
2.4
2.2
2.0
1.8
1.6
1.4
1.2
I
D
= 250 µA
30
20
10
0
0.001
1
0.0001
0.01
0.1
10
100 1000
– 50
– 25
0
25
50
75
100 125 150
T
–
T
e
mperature (°C)
J
Time (s)
Single Pulse Power
Threshold Voltage
10
Limited by R
*
DS(on)
100 µs
1
1 ms
10 ms
0.1
100 ms
1 s, 10 s
DC
T
= 25 °C
A
Single Pulse
BVDSS
Limited
0.01
0.01
0.1
DS
1
10
100
V
– Drain-to-Source Voltage (V)
* V
GS
minimum V
at which R
is specified
DS(on)
GS
Safe Operating Area, Junction-to-Ambient
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
5
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
6
5
4
3
2
1
0
4
3
2
1
0
Package Limited
0
25
50
75
100
125
150
25
50
75
100
125
150
T
– Case
T
e
mperature (°C)
T
– Case
T
e
mperature (°C)
C
C
Current Derating*
Power Derating
* The power dissipation P
D
is based on T
(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
6
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
N-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
2
1
Duty Cycle = 0.5
0.2
Notes:
P
DM
0.1
0.1
t
0.05
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
= 1
00
°C/W
thJA
(t)
3. T
– T
= P
JM
Z
A
DM thJA
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
7
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
10
5
4
3
2
1
0
V
GS
= 10 V thru 5 V
8
6
4 V
4
T
= 125 °C
25 °C
C
2
3 V
– 55 °C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
V
DS
– Drain-to-Source Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.4
0.3
0.2
0.1
0.0
250
200
150
100
50
C
iss
V
GS
= 4.5 V
V
= 10 V
GS
C
oss
C
rss
0
0
2
4
6
8
10
0
5
10
15
20
25
30
I
D
– Drain Current (A)
V
DS
– Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
10
8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
V
D
= 4.5
V
,
1
0 V
GS
I =
2.2 A
I
D
= 2.5 A
V
DS
= 15 V
6
V
DS
= 24 V
4
2
0
0
1
2
3
4
5
– 50
– 25
0
25
50
75
100 125 150
Q
–
T
o
tal Gate Charge (nC)
T –
Junction
T
e
mperature (°C)
J
g
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 74483
S13-2463-Rev. C, 02-Dec-13
8
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
0.4
0.3
0.2
0.1
0.0
10
I
D
= 2.2
A
125 °C
T
= 150 °C
J
T
= 25 °C
J
25 °C
1
0.0
2
4
6
8
10
0.2
0.4
0.6
0.8
1.0
1.2
V
SD
– Source-to-Drain Voltage (V)
V
GS
– Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
50
40
I
D
= 250 µA
30
20
10
0
– 50
– 25
0
25
50
75
100 125 150
0.001
1
0.0001
0.01
0.1
10
100 1000
T
–
T
e
mperature (°C)
Time (s)
Single Pulse Power
J
Threshold Voltage
10
Limited by R
*
DS(on)
100 µs
1 ms
1
10 ms
0.1
100 ms
1 s, 10 s
DC
T
= 25 °C
A
Single Pulse
BVDSS
Limited
0.01
0.01
0.1
1
10
100
V
DS
– Drain-to-Source Voltage (V)
* V
GS
minimum V
at which R
is specified
GS
DS(on)
Safe Operating Area, Junction-to-Ambient
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
9
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
4
3
2
1
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
– Case
T
e
mperature (°C)
T
– Case
T
e
mperature (°C)
C
C
Current Derating*
Power Derating
* The power dissipation P
D
is based on T
J(max.)
= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
10
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Si5504BDC
Vishay Siliconix
P-CHANNEL TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
2
1
Duty Cycle = 0.5
0.2
Notes:
P
DM
0.1
0.1
t
0.05
1
t
2
t
t
1
2
1. Duty Cycle, D =
0.02
2. Per Unit Base = R
=
100 °
C/W
thJA
(t)
3. T
– T
= P
Z
JM
A
DM thJA
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
S13-2463-Rev. C, 02-Dec-13
Document Number: 74483
11
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Package Information
Vishay Siliconix
1206-8 ChipFET
R
4
L
D
8
1
7
2
6
3
5
4
5
4
6
3
7
2
8
1
4
E
1
E
x
S
e
b
c
Backside View
2X 0.10/0.13 R
A
DETAIL X
NOTES:
1. All
dimensions are in millimeaters.
2. Mold
gate burrs shall not exceed 0.13 mm per side.
3. Leadframe
to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4. Dimensions
exclusive of mold gate burrs.
5. No
mold flash allowed on the top and bottom lead surface.
MILLIMETERS
INCHES
Min Nom Max
Dim
A
b
c
c1
D
E
E
1
e
Min
1.00
0.25
0.1
Nom
−
Max
1.10
0.039
0.010
0.004
0
−
0.012
0.006
−
0.043
0.014
0.008
0.0015
0.122
0.078
0.067
0.30
0.35
0.15
0.20
0
−
0.038
3.10
2.95
1.825
1.55
3.05
0.116
0.072
0.061
0.120
0.075
0.065
0.0256 BSC
−
1.90
1.975
1.70
1.65
0.65 BSC
−
0.28
0.42
0.0
1
1
0.017
L
0.55 BSC
5
_
Nom
0.022 BSC
5
_
Nom
S
ECN: C-03528—Rev.
F
,
1
9-Jan-04
DWG: 5547
Document Number:
71151
15-Jan-04
1
AN812
Vishay Siliconix
Dual-Channel 1206-8 ChipFET
r
Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFE
T
s
i
n the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
80 mil
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOT
R
TSOP-6, and can
25 mil
18 mil
43 mil
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
This technical note discusses the dual ChipFET 1206-8
pin-out, package outline, pad patterns, evaluation board
layout, and thermal performance.
10 mil
26 mil
PIN-OUT
FIGURE 2.
Footprint With Copper Spreading
Figure 1
shows the pin-out description and Pin 1 identification
for the dual-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thus thermal
performance. The legs of the device are very short, again
helping to reduce the thermal path to the external heatsink/pcb
and allowing a larger die to be fitted in the device if necessary.
The pad pattern with copper spreading shown in Figure
2
improves the thermal area of the drain connections (pins 5 and
6, pins 7 and 8) while remaining within the confines of the basic
footprint. The drain
copper area is 0.0019 sq. in. or
1.22 sq. mm. This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the dual device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the Vishay
Siliconix Evaluation Board described in the next section
(Figure 3).
Dual 1206-8 ChipFET
S
1
G
1
S
2
G
2
D
1
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE DUAL 1206-8
D
1
D
2
D
2
The dual ChipFET 1206-08 evaluation board measures 0.6 in
by 0.5 in. Its copper pad pattern consists of an increased pad
area around each of the two drain leads on the top-side—
approximately 0.0246 sq. in. or 15.87 sq. mm—and vias
added through to the underside of the board, again with a
maximized copper pad area of approximately the board-size
dimensions, split into two for each of the drains. The outer
package outline is for the 8-pin DI
P
,
w
hich will allow test
sockets to be used to assist in testing.
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826,
Recommended Minimum Pad Patterns With Outline
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
Drawing
Access
for
Vishay Siliconix
MOSFE
T
s,
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number:
71127
12-Dec-03
1
AN812
Vishay Siliconix
Front of Board
Back of Board
ChipFET
r
vishay.com
FIGURE 3.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 57
_
C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 38
_
C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
PCB.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance (the Package
Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 30
_
C/W typical, 40
_
C/W
maximum for the dual device. The “foot” is the drain lead of the
device as it connects with the body. This is identical to the dual
SO-8 package R
Q
jf
performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
200
Min. Footprint
160
Dual EVB
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
120
The typical R
Q
ja
for the dual-channel 1206-8 ChipFET is
90
_
C/W steady state, identical to the SO-8. Maximum ratings
are
1
1
0
_
C/W for both the 1206-8 and the SO-8. Both packages
have comparable thermal performance on the 1” square pcb
footprint with the 1206-8 dual package having a quarter of the
body area, a significant factor when considering board area.
80
40
1” Square PCB
Testing
0
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
dual thermal performance on two different board sizes and
three different pad patterns.The results display the thermal
performance out to steady state and produce a graphic
account on how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of R
Q
ja
for the Dual 1206-8
ChipFET are :
-5
-4
-3
-2
-1
10
10
10
10
10
Time (Secs)
1
10
100
1000
FIGURE 4.
Dual 1206-8 ChipFET
SUMMARY
The thermal results for the dual-channel 1206-8 ChipFET
package display identical power dissipation performance to
the SO-8 with a footprint reduction of 80%. Careful design of
the package has allowed for this performance to be achieved.
The short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
1) Minimum recommended pad pattern (see
185
_
C/W
Figure 2)
on the evaluation board size of
0.5 in x 0.6 in.
2) The evaluation board with the pad pattern
128
_
C/W
described on Figure
3.
ASSOCIATED DOCUMENT
3) Industry standard 1” square pcb with
maximum copper both sides.
90
_
C/W
1206-8 ChipFET Single Thermal performance, AN811,
Document Number:
71127
12-Dec-03
2
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Revision: 01-Jan-2019
Document Number: 91000
1
