Vishay-Intertech-SIRA88DP-T1-GE3
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SiRA88DP
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
FEATURES
• TrenchFET
®
Gen IV power MOSFET
PowerPAK
®
S
O-8
S
ingle
D
D
7
8
D
6
• 100 % R
g
and UIS tested
D
5
• Material categorization:
for definitions of compliance please see
1
S
APPLICATIONS
• DC/DC conversion
• Battery protection
• Load switching
2
S
D
3
4
G
S
1
Top View
Bottom View
PRODUCT SUMMARY
V
DS
(V)
G
• DC/AC inverters
30
R
DS(on)
max. (
Ω
) at V
GS
= 10 V
DS(on)
max. (
Ω
) at V
GS
= 4.5 V
0.0067
0.0100
8.3
R
S
Q
g
typ. (nC)
D
(A)
Configuration
N-Channel MOSFET
I
45.5
Single
ORDERING INFORMATION
Package
PowerPAK SO-8
Lead (Pb)-free and halogen-free
SiRA88DP-T1-GE3
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
30
UNIT
Drain-source voltage
Gate-source voltage
V
DS
V
V
GS
+20, -16
45.5
T
C
= 25 °C
C
= 70 °C
T
36.4
Continuous drain current (T
J
= 150 °C)
I
D
T
A
= 25 °C
T
A
= 70 °C
16.5
b, c
13.1
b, c
100
A
Pulsed drain current (t = 300 μs)
I
DM
I
S
T
C
= 25 °C
22.7
3
b, c
Continuous source-drain diode current
T
A
= 25 °C
L = 0.1 mH
T
C
= 25 °C
Single pulse avalanche current
Single pulse avalanche energy
I
AS
10
E
AS
5
mJ
W
25
T
C
= 70 °C
16
Maximum power dissipation
P
D
T
A
= 25 °C
T
A
= 70 °C
3.3
b, c
2.1
b ,c
-55 to +150
260
Operating junction and storage temperature range
Soldering recommendations (peak temperature)
d, e
T
J
, T
stg
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum junction-to-ambient
b, f
SYMBOL
R
thJA
TYPICAL
MAXIMUM
UNIT
t
≤
10 s
Steady state
30
4
37
5
°C/W
Maximum junction-to-case (drain)
R
thJC
Notes
a. Based
on T
C
= 25 °C
b. Surface
mounted on 1″ x 1″ FR4 board
c. t
= 10 s
d. See
solder profile (
www.vishay.com/doc?73257
). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a re
sult of the singulation proces
s in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection
e. Rework
conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum
under steady state conditions is 70 °C/W
S17-0792-Rev. B, 22-May-17
Document Number: 77777
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SiRA88DP
Vishay Siliconix
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
V
DS
V
GS
= 0 V, I
D
= 250 μA
30
36
–
–
–
–
V
Drain-source breakdown voltage
(transient)
c
V
DSt
V
GS
= 0 V, I
D(aval)
= 10 A, t
transcient
≤
50 ns
V
DS
temperature coefficient
Δ
V
DS
/T
J
Δ
V
GS(th)
/T
J
V
GS(th)
–
–
15.5
–
I
D
= 250 μA
mV/°C
V
GS(th)
temperature coefficient
Gate-source threshold voltage
Gate-source leakage
-4.7
–
V
DS
= V
GS
, I
D
= 250 μA
V
DS
= 0 V, V
GS
= +20, -16 V
V
DS
= 30 V, V
GS
= 0 V
1.1
–
–
2.4
V
I
GSS
–
100
nA
–
–
1
Zero gate voltage drain current
On-state drain current
a
I
DSS
I
D(on)
R
DS(on)
g
fs
μA
A
V
DS
= 30 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
≥
5 V, V
GS
= 10 V
–
–
–
10
30
–
–
V
GS
= 10 V, I
D
= 10 A
0.0054
0.0078
47
0.0067
0.0100
–
Drain-source on-state resistance
a
Ω
S
V
GS
= 4.5 V, I
D
= 8 A
–
Forward transconductance
a
Dynamic
b, d
V
DS
= 10 V, I
D
= 10 A
–
Input capacitance
C
iss
C
oss
C
rss
–
–
985
305
38
–
–
Input capacitance
V
DS
= 15 V, V
GS
= 0 V, f = 1 MHz
V
DS
= 15 V, V
GS
= 10 V, I
D
= 10 A
pF
Output capacitance
Reverse transfer capacitance
–
–
–
0.039
16.8
8.3
2.1
2.8
8.7
1.7
7
0.078
25.5
12.5
–
C
rss
/C
iss
ratio
–
Q
g
–
Total gate charge
Q
gs
Q
gd
Q
oss
R
g
V
DS
= 15 V, V
GS
= 4.5 V, I
D
= 10 A
–
nC
Gate-source charge
–
–
Gate-drain charge
V
DS
= 15 V, V
GS
= 0 V
f = 1 MHz
–
–
Output charge
0.8
–
3.1
14
56
28
16
22
94
36
36
Ω
Gate resistance
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Turn-on delay time
–
28
V
DD
= 15 V, R
L
= 1.5
Ω
I
D
≅
10 A, V
GEN
= 10 V, R
g
= 1
Ω
Rise time
–
14
Turn-off delay time
–
8
ns
Fall time
–
11
Turn-on delay time
–
47
V
DD
= 15 V, R
L
= 1.5
Ω
I
D
≅
10 A, V
GEN
= 4.5 V, R
g
= 1
Ω
Rise time
–
18
Turn-off delay time
–
18
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulse diode forward current
a
Body diode voltage
I
S
I
SM
V
SD
t
rr
T
C
= 25 °C
I
S
= 5 A
–
–
–
–
–
–
–
–
–
22.7
100
1.1
96
140
–
A
0.77
48
72
40
8
V
Body diode reverse recovery time
Body diode reverse recovery charge
Reverse recovery fall time
Reverse recovery rise time
ns
nC
Q
rr
t
a
I
F
= 10 A, di/dt = 100 A/μs,
T
J
= 25 °C
ns
t
b
–
Notes
a. Pulse
test; pulse width
≤
300 μs, duty cycle
≤
2 %
b. Guaranteed
by design, not subject to production testing
c. T
C
= 25 °C; expected voltage stress during 100 % UIS test. Production data log is not available
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S17-0792-Rev. B, 22-May-17
Document Number: 77777
2
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SiRA88DP
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Axis Title
Axis Title
100
80
60
40
20
0
10000
1000
100
80
64
48
32
16
0
10000
1000
100
V
GS
= 10 V thru 5 V
V
GS
= 4 V
V
GS
= 3 V
T
C
= 25 °C
T
C
= 125 °C
T
C
= -55 °C
V
GS
= 2 V
10
10
0
0
0
0.5
1
1.5
2
2.5
100
20
0
1
2
3
4
5
V
DS
– Drain-to-Source Voltage (V)
2nd line
V
GS
– Gate-to-Source Voltage (V)
2nd line
Output Characteristics
Transfer Characteristics
Axis Title
Axis Title
0.020
0.016
0.012
0.008
0.004
0
10000
1000
100
1300
1040
780
520
260
0
10000
1000
100
C
iss
V
GS
= 4.5 V
C
oss
V
GS
= 10 V
C
rss
10
10
20
40
60
80
0
5
10
15
20
25
30
I
D
– Drain Current (A)
2nd line
V
DS
– Drain-to-Source Voltage (V)
2nd line
On-Resistance vs. Drain Current
Capacitance
Axis Title
Axis Title
10
8
10000
1000
100
1.7
1.5
1.3
1.1
0.9
0.7
10000
1000
100
I
D
= 10 A
I
D
= 10 A
V
GS
= 10 V
6
V
GS
= 4.5 V
4
V
DS
= 10 V, 15 V, 20 V
2
0
10
10
4
8
12
16
-50 -25
0
25
50
75 100
125 150
Q
g
– Total Gate Charge (nC)
2nd line
T
J
– Junction Temperature (°C)
2nd line
Gate Char
g
e
On-Resistance vs. Junction Temperature
S17-0792-Rev. B, 22-May-17
Document Number: 77777
3
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SiRA88DP
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Axis Title
Axis Title
100
10
10000
1000
100
0.030
0.024
0.018
0.012
0.006
0.000
10000
1000
T
J
= 150 °C
1
T
J
= 25 °C
T
J
= 125 °C
0.1
100
10
0.01
0.001
T
J
= 25 °C
8
10
0
0.2
0.4
0.6
0.8
1.0
1.2
0
2
4
6
10
V
SD
– Source-to-Drain Voltage (V)
2nd line
V
GS
– Gate-to-Source Voltage (V)
2nd line
Source-Drain Diode Forward Volta
g
e
On-Resistance vs. Gate-to-Source Volta
g
e
Axis Title
Axis Title
0.5
0.2
10000
1000
100
200
160
120
80
10000
1000
100
10
-0.1
-0.4
-0.7
-1.0
I
D
= 5 mA
I
D
= 250 μA
40
10
0
-50 -25
0
25
50
75 100
125 150
0.001
0.01
0.1
1
10
T
J
– Temperature (°C)
2nd line
Time (s)
2nd line
Threshold Volta
g
e
Sin
g
le Pulse Power, Junction-to-Ambient
Axis Title
1000
100
10
10000
I
DM
limited
100 μs
1000
I
D
limited
1 ms
10 ms
100 ms
1 s
10 s
1
(1)
Limited by R
DS(on)
100
0.1
0.01
DC
T
A
= 25 °C
Single pulse
BVDSS limited
10
10
0.01
0.1
1
100
V
DS
– Drain-to-Source Voltage (V)
> minimum V
GS
at which R
DS(on)
is specified
(1)
V
GS
Safe Operatin
g
Area
S17-0792-Rev. B, 22-May-17
Document Number: 77777
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SiRA88DP
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Axis Title
50
10000
1000
100
40
30
20
10
0
10
0
25
50
75
100
125
150
T
C
– Case Temperature (°C)
2nd line
Current Deratin
g
a
Axis Title
Axis Title
30
24
18
12
6
10000
1000
100
2.5
2.0
1.5
1.0
0.5
0
10000
1000
100
0
10
10
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
C
– Case Temperature (°C)
2nd line
T
A
– Ambient Temperature (°C)
2nd line
Power, Junction-to-Case
Power, Junction-to-Ambient
Note
a. The
power dissipation P
D
is based on T
J
max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit
S17-0792-Rev. B, 22-May-17
Document Number: 77777
5
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SiRA88DP
Vishay Siliconix
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Axis Title
1
10000
1000
100
Duty cycle = 0.5
0.2
0.1
Notes:
P
DM
0.1
0.05
t
1
t
2
1. Duty cycle, D =
t
1
t
2
0.02
2. Per unit base = R
thJA
= 70 °C/W
(t)
3. T
JM
– T
A
= P
DM
Z
thJA
Single pulse
0.01
4. Surface mounted
0.01
0.0001
10
1000
0.001
0.1
1
10 100
Square Wave Pulse Duration (s)
2nd line
Normalized Thermal Transient Impedance, Junction-to-Ambient
Axis Title
1
10000
1000
100
Duty cycle = 0.5
0.2
0.1
0.05
0.1
0.02
Single pulse
0.01
0.0001
10
0.001
0.01
0.1
1
10
Square Wave Pulse Duration (s)
2nd line
Normalized Thermal Transient Impedance, Junction-to-Case
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
S17-0792-Rev. B, 22-May-17
Document Number: 77777
6
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Package Information
Vishay Siliconix
PowerPAK
®
SO-8, (Single/Dual)
L
H
E2
K
E4
W
1
1
2
3
4
Z
2
3
4
D
L1
E3
A1
Backside View of Single Pad
L
H
K
E2
E4
2
E1
E
Detail Z
1
2
3
4
D1
D2
Notes
1. Inch will govern.
E3
2
Dimensions exclusive of mold gate burrs.
Backside View of Dual Pad
3.
Dimensions exclusive of mold flash and cutting burrs.
MILLIMETERS
INCHES
NOM.
0.041
DIM.
MIN.
NOM.
1.04
MAX.
1.12
0.05
0.51
0.33
5.26
5.00
3.91
1.68
MIN.
0.038
0
MAX.
0.044
0.002
0.020
0.013
0.207
0.197
0.154
0.066
A
A1
b
0.97
–
–
0.33
0.23
5.05
4.80
3.56
1.32
0.41
0.013
0.009
0.199
0.189
0.140
0.052
0.016
c
0.28
0.011
D
5.15
0.203
D1
D2
D3
D4
D5
E
4.90
0.193
3.76
0.148
1.50
0.059
0.57 typ.
3.98 typ.
6.15
0.0225 typ.
0.157 typ.
0.242
6.05
5.79
3.48
3.68
6.25
5.99
3.84
3.91
0.238
0.228
0.137
0.145
0.246
0.236
0.151
0.154
E1
E2
E3
E4
e
5.89
0.232
3.66
0.144
3.78
0.149
0.75 typ.
1.27 BSC
1.27 typ.
–
0.030 typ.
0.050 BSC
0.050 typ.
–
K
K1
H
0.56
0.51
0.51
0.06
0°
–
0.022
0.020
0.020
0.002
0°
–
0.61
0.71
0.71
0.20
12°
0.024
0.028
0.028
0.008
12°
L
0.61
0.024
L1
0.13
0.005
–
–
W
M
0.15
0.25
0.36
0.006
0.010
0.014
0.125 typ.
0.005 typ.
ECN: S17-0173-Rev. L, 13-Feb-17
DWG: 5881
Revison: 13-Feb-17
Document Number: 71655
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
VISHAY SILICONIX
Power MOSFETs
Application Note AN821
PowerPAK
®
SO-8 Mounting and Thermal Considerations
by Wharton McDaniel
PowerPAK SO-8 SINGLE MOUNTING
MOSFETs for switching applications are now available with
die on resistances around 1 m
and with the capability to
handle 85 A. While these die capabilities represent a major
advance over what was available just a few years ago, it is
important for power MOSFET packaging technology to keep
pace. It should be obvious that degradation of a high
performance die by the package is undesirable. PowerPAK
is a new package technology that addresses these issues.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.
The PowerPAK single is simple to use. The pin arrangement
(drain, source, gate pins) and the pin dimensions are the
same as standard SO-8 devices (see figure 2). Therefore, the
PowerPAK connection pads match directly to those of the
SO-8. The only difference is the extended drain connection
area. To take immediate advantage of the PowerPAK SO-8
single devices, they can be mounted to existing SO-8 land
patterns.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly
larger than a full sized DPAK die. The bottom of the die
attach pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device is
mounted on. Finally, the package height is lower than the
standard SO-8, making it an excellent choice for
applications with space constraints.
Standard SO-8
Po
w
er
P
A
K SO-8
Fig. 2
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826,
Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs
. Click on the PowerPAK SO-8 single in the index
of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
from the foot of the PowerPAK to the PC board and
therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in
2
to 0.5 in
2
of additional copper
(in addition to the drain land) will yield little improvement in
thermal performance.
Fig. 1
PowerPAK 1212 Devices
Revision: 16-Mai-13
Document Number: 71622
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Application Note AN821
Vishay Siliconix
PowerPAK
®
SO-8 Mounting and Thermal Considerations
For
the
lead
(Pb)-free
solder
profile,
see
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the pin
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs
. Click on the
PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the
PowerPAK SO-8 dual package.
Fig. 3
Solder Reflow Temperature Profile
Ramp-Up Rate
+ 3 °C /s max.
120 s max.
REFLOW SOLDERING
Temperature at 150 – 200 °C
Temperature Above 217 °C
Maximum Temperature
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder
60 – 150 s
255 + 5/- 0 °C
reflow as
a
test preconditioning and are then
reliability-tested using temperature cycle, bias humidity,
HAST, or pressure pot. The solder reflow temperature profile
used, and the temperatures and time duration, are shown in
figures 3 and 4.
Time at Maximum
Temperature
30 s
Ramp-Down Rate
+ 6 °C/s max.
30 s
260 °C
3 °C(max)
6 °C/s (max.)
217 °C
150 – 200 °C
150 s (max.)
60 s (min.)
Reflo
w
Zone
Pre-Heating Zone
Maxim
u
m peak temperat
u
re at 240 °C is allo
w
ed.
Fig. 4
Solder Reflow Temperatures and Time Durations
Revision: 16-Mai-13
Document Number: 71622
2
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Application Note AN821
Vishay Siliconix
PowerPAK
®
SO-8 Mounting and Thermal Considerations
THERMAL PERFORMANCE
Introduction
Because of the presence of the trough, this result suggests
a minimum performance improvement of 10 °C/W by using
a PowerPAK SO-8 in a standard SO-8 PC board mount.
A basic measure of a device’s thermal performance
is the junction-to-case thermal resistance, R
thJC
, or the
junction-to-foot thermal resistance, R
thJF
This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which
the device is mounted. Table 1 shows a comparison of
the DPAK, PowerPAK SO-8, and standard SO-8. The
PowerPAK has thermal performance equivalent to the
DPAK, while having an order of magnitude better thermal
performance over the SO-8.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no traces
running between the body of the MOSFET. Where the
standard SO-8 body is spaced away from the pc board,
allowing traces to run underneath, the PowerPAK sits
directly on the pc board.
Thermal Performance – Spreading Copper
Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
helpful to have some information about the thermal
performance for a given area of spreading copper.
TABLE 1 – DPAK AND POWERPAK SO-8
EQUIVALENT STEADY STATE
PERFORMANCE
Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
The two internal layers and the backside layer are solid
copper. The internal layers were chosen as solid copper to
model the large power and ground planes common in many
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an area
above 0.3 to 0.4 square inches of spreading copper gives no
PowerPAK
SO-8
Standard
SO-8
DPAK
Thermal
Resistance R
thJC
1.2 °C/W
1 °C/W
16 °C/W
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pattern.
The question then arises as to the thermal performance
of the PowerPAK device under these conditions. A
characterization was made comparing a standard SO-8 and
a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results
are shown in figure 5.
additional
thermal
performance
improvement.
A
subsequent experiment was run where the copper on the
back-side was reduced, first to 50 % in stripes to mimic
circuit traces, and then totally removed. No significant effect
was observed.
R
th
v
s. Spreading Copper
(0 %, 50 %, 100 % Back Copper)
56
51
46
41
36
Si4874DY
v
s. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Tro
u
gh Under Drain
60
50
40
Si4874DY
30
100 %
Si7446DP
0 %
20
50 %
10
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Spreading Copper (sq in)
0
Fig. 6
Spreading Copper Junction-to-Ambient Performance
0.0001
0.01
1
10000
100
P
u
lse D
u
ration (sec)
Fig. 5
PowerPAK SO-8 and Standard SO-0 Land Pad Thermal
Path
Revision: 16-Mai-13
Document Number: 71622
3
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Application Note AN821
Vishay Siliconix
PowerPAK
®
SO-8 Mounting and Thermal Considerations
Suppose each device is dissipating 2.7 W. Using the
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
temperature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
and a 43 °C rise for the standard SO-8. Referring to figure 7,
a 2 °C difference has minimal effect on R
DS(on)
whereas a
In any design, one must take into account the change in
MOSFET R
DS(on)
with temperature (figure 7).
On-Resistance
v
s. J
u
nction
T
e
mperat
u
re
1.8
43 °C difference has a significant effect on R
DS(on)
.
V
= 10 V
= 23
A
GS
1.6
1.4
1.2
1.0
0.8
0.6
I
D
Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
it has allowed the device to run cooler, keep r
DS(on)
low, and
permits the device to handle more current than the same
MOSFET die in the standard SO-8 package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same thermal
performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
SO-8 can hold larger die approximately equal in size to the
maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.
–
5
0
–
2
5
0
25
50
75
100 125 150
T
J
– J
u
nction
T
e
mperat
u
re (°C)
Recommended PowerPAK SO-8 land patterns are provided
to aid in PC board layout for designs using this new
package.
Fig. 7
MOSFET R
DS(on)
vs. Temperature
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises the
junction temperature of the device above that of the PC
board to which it is mounted, causing increased power
dissipation in the device. A major source of this problem lies
in the large values of the junction-to-foot thermal resistance
of the SO-8 package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and
typical thermal performance in a SO-8 environment, plus
information on the optimum thermal performance
obtainable including spreading copper. This further
emphasized the DPAK equivalency.
PowerPAK SO-8 minimizes the junction-to-board thermal
resistance to where the MOSFET die temperature is very
close to the temperature of the PC board. Consider two
devices mounted on a PC board heated to 105 °C by other
components on the board (figure 8).
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
Po
w
erPAK SO-8
Standard SO-8
107 °C
148 °C
0.8 °C/W
PC Board at 105 °C
16 C/W
Fig. 8
Temperature of Devices on a PC Board
Revision: 16-Mai-13
Document Number: 71622
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM
P
A
DS FOR Power
P
A
K
®
SO-8 Single
0.260
(6.61)
0.150
(3.81)
0.024
(0.61)
0.026
(0.66)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72599
Revision: 21-Jan-08
15
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Document Number: 91000
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