Vishay-Intertech-SQS484ENW-T1-GE3
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SQS484ENW
Vishay Siliconix
Automotive N-Channel 40 V (D-S) 175 °C MOSFET
FEATURES
• TrenchFET
®
power MOSFET
PowerPAK
®
1212-8W
S
ingle
D
8
D
7
D
6
• AEC-Q101 qualified
D
5
• 100 % R
g
and UIS tested
• Material categorization:
for definitions of compliance please see
1
2
S
S
3
D
G
1
Top View
Bottom View
PRODUCT SUMMARY
G
V
DS
(V)
40
R
DS(on)
(
) at V
GS
= 10 V
DS(on)
(
) at V
GS
= 4.5 V
0.0080
0.0105
16
R
S
I
D
(A)
Configuration
Package
Single
N-Channel MO
S
FET
PowerPAK 1212-8W
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-source voltage
Gate-source voltage
V
DS
40
V
V
GS
20
T
C
= 25 °C
16
16
Continuous drain current
a
I
D
T
C
= 125 °C
Continuous source current (diode conduction)
a
Pulsed drain current
b
I
S
16
A
I
DM
I
AS
64
Single pulse avalanche current
Single pulse avalanche energy
25
L = 0.1 mH
E
AS
31.2
62.5
20
mJ
W
T
C
= 25 °C
Maximum power dissipation
b
P
D
T
C
= 125 °C
Operating junction and storage temperature range
Soldering recommendations (peak temperature)
e, f
T
J
, T
stg
-55 to +175
260
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
R
thJA
LIMIT
81
UNIT
Junction-to-ambient
PCB mount
c
°C/W
Junction-to-case (drain)
R
thJC
2.4
Notes
a. Package
limited.
b. Pulse
test; pulse width
300 μs, duty cycle
2 %.
c. When
mounted on 1″ square PCB (FR4 material).
d. Parametric
verification ongoing.
e. See
solder profile (
www.vishay.com/doc?73257
). The PowerPAK 1212-8W is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
f. Rework
conditions: manual soldering with a soldering iron is not recommended for leadless components.
S16-2192-Rev. A, 24-Oct-16
Document Number: 62896
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SQS484ENW
Vishay Siliconix
SPECIFICATIONS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
Gate-source threshold voltage
Gate-source leakage
V
DS
V
GS(th)
I
GSS
V
GS
= 0, I
D
= 250 μA
40
1.5
–
–
2.0
–
–
2.5
100
1
V
V
DS
= V
GS
, I
D
= 250 μA
V
DS
= 0 V, V
GS
=
20 V
nA
V
GS
= 0 V
V
DS
= 40 V
–
–
Zero gate voltage drain current
On-state drain current
a
I
DSS
V
GS
= 0 V
GS
= 0 V
V
DS
= 40 V, T
J
= 125 °C
V
DS
= 40 V, T
J
= 175 °C
V
DS
5 V
–
–
50
150
–
μA
A
V
–
–
I
D(on)
V
GS
= 10 V
20
–
–
V
GS
= 10 V
V
GS
= 10 V
V
GS
= 10 V
I
D
= 10 A
0.0065 0.0080
I
D
= 10 A, T
J
= 125 °C
I
D
= 10 A, T
J
= 175 °C
I
D
= 10 A
–
–
–
0.0113
0.0133
Drain-source on-state resistance
a
R
DS(on)
–
V
GS
= 4.5 V
–
0.0085 0.0105
Forward transconductance
b
Dynamic
b
g
fs
V
DS
= 15 V, I
D
= 10 A
–
52
–
S
Input capacitance
Output capacitance
Reverse transfer capacitance
Total gate charge
c
Gate-source charge
c
Gate-drain charge
c
Gate resistance
Turn-on delay time
c
Rise time
c
Turn-off delay time
c
Fall time
c
C
iss
C
oss
C
rss
Q
g
–
1380
850
40
22
4
1800
1110
60
V
GS
= 0 V
V
DS
= 25 V, f = 1 MHz
–
pF
–
–
35
Q
gs
Q
gd
R
g
V
GS
= 10 V
V
DS
= 20 V, I
D
= 4 A
f = 1 MHz
–
–
nC
–
3
–
0.48
0.97
11
5
1.50
20
t
d(on)
t
r
t
d(off)
t
f
–
–
–
–
10
V
DD
= 20 V, R
L
= 5
ns
I
D
4 A, V
GEN
= 10 V, R
g
= 1
25
10
40
20
Source-Drain Diode Ratin
g
s and Characteristic
b
Pulsed current
a
I
SM
V
SD
t
rr
–
–
–
–
–
–
–
–
64
1.1
90
90
–
A
V
Forward voltage
I
F
= 10 A, V
GS
= 0 V
0.82
44
Body diode reverse recovery time
Body diode reverse recovery charge
Reverse recovery fall time
Reverse recovery rise time
Body diode peak reverse recovery current
ns
nC
Q
rr
42
I
F
= 5 A, dI/dt = 100 A/μs
t
a
22
ns
A
t
b
25
–
I
RM(REC)
-1.8
-4
Notes
a. Pulse
test; pulse width
300 μs, duty cycle
2 %.
b. Guaranteed
by design, not subject to production testing.
c. Independent
of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S16-2192-Rev. A, 24-Oct-16
Document Number: 62896
2
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SQS484ENW
Vishay Siliconix
TYPICAL CHARACTERISTICS
(T
A
= 25 °C, unless otherwise noted)
Axis Title
Axis Title
80
64
48
32
16
0
10000
1000
100
80
64
48
32
16
0
10000
1000
100
V
GS
= 10 V thru 4 V
T
C
= 25 °C
T
C
= 125 °C
V
GS
= 3 V
T
C
= -55 °C
4
10
10
0
0
0
2
4
6
8
10
25
40
0
0
0
2
6
8
10
60
25
V
DS
– Drain-to-Source Voltage (V)
2nd line
V
GS
– Gate-to-Source Voltage (V)
2nd line
Output Characteristics
Transfer Characteristics
Axis Title
Axis Title
100
80
60
40
20
0
10000
1000
100
0.025
0.020
0.015
0.010
0.005
0.000
10000
1000
100
T
C
= -55 °C
T
C
= 25 °C
T
C
= 125 °C
V
GS
= 4.5 V
V
GS
= 10 V
10
10
5
10
15
20
12
24
36
48
I
D
– Drain Current (A)
2nd line
I
D
– Drain Current (A)
2nd line
Transconductance
On-Resistance vs. Drain Current
Axis Title
Axis Title
3000
2400
1800
1200
600
10000
1000
100
10
8
10000
1000
100
I
D
= 4 A
DS
= 20 V
V
6
C
iss
4
C
oss
2
C
rss
0
10
0
10
8
16
24
32
5
10
15
20
V
DS
– Drain-to-Source Voltage (V)
2nd line
Q
g
– Total Gate Charge (nC)
2nd line
Capacitance
Gate Char
g
e
S16-2192-Rev. A, 24-Oct-16
Document Number: 62896
3
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SQS484ENW
Vishay Siliconix
TYPICAL CHARACTERISTICS
(T
A
= 25 °C, unless otherwise noted)
Axis Title
Axis Title
2.0
1.7
1.4
1.1
0.8
0.5
10000
1000
100
100
10
10000
1000
I
D
= 6 A
V
GS
= 10 V
T
J
= 150 °C
1
V
GS
= 4.5 V
T
J
= 25 °C
0.1
100
0.01
0.001
10
10
-50 -25
0
25 50 75
100 125 150 175
0
0.2
0.4
0.6
0.8
1.0
1.2
T
J
– Junction Temperature (°C)
2nd line
V
SD
– Source-to-Drain Voltage (V)
2nd line
On-Resistance vs. Junction Temperature
Source Drain Diode Forward Volta
g
e
Axis Title
Axis Title
0.05
0.04
0.03
0.02
0.01
0.00
10000
1000
100
0.5
0.2
10000
1000
100
-0.1
-0.4
-0.7
-1.0
I
D
= 5 mA
T
J
= 150 °C
I
D
= 250 μA
T
J
= 25 °C
10
10
0
2
4
6
8
10
-50 -25
0
25 50 75
100 125 150 175
V
GS
– Gate-to-Source Voltage (V)
2nd line
T
J
– Temperature (°C)
2nd line
On-Resistance vs. Gate-to-Source Volta
g
e
Threshold Volta
g
e
Axis Title
55
10000
1000
100
I
D
= 1 mA
52
49
46
43
40
10
-50 -25
0
25 50 75
100 125 150 175
T
J
– Junction Temperature (°C)
2nd line
Drain Source Breakdown vs. Junction Temperature
S16-2192-Rev. A, 24-Oct-16
Document Number: 62896
4
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SQS484ENW
Vishay Siliconix
THERMAL RATINGS
(T
A
= 25 °C, unless otherwise noted)
Axis Title
I
DM
limited
1000
10000
1000
100
100 μs
10
1 ms
10 ms
I
D
limited
100 ms, 1 s, 10 s, DC
100
1
(1)
Limited by R
DS(on)
0.1
T
C
= 25 °C
Single pulse
BVDSS limited
10
0.01
10
1000
0.01
0.1
1
100
V
DS
– Drain-to-Source Voltage (V)
> minimum V
GS
at which R
DS(on)
is specified
(1)
V
GS
Safe Operatin
g
Area
1
Duty cycle = 0.5
0.2
0.1
Notes:
0.1
P
DM
0.05
t
1
t
2
t
t
1
2
0.02
1. Duty cycle, D =
2. Per unit base = R
= 81 °C/W
thJA
(t)
Z
3. T
– T
= P
DM thJA
JM
A
Single pulse
4. Surface mounted
0.01
-4
-3
-2
-1
10
10
10
10
1
100
1000
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
S16-2192-Rev. A, 24-Oct-16
Document Number: 62896
5
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
SQS484ENW
Vishay Siliconix
THERMAL RATINGS
(T
A
= 25 °C, unless otherwise noted)
2
1
D
u
ty cycle = 0.5
0.2
0.1
0.1
Single p
u
lse
0.05
0.02
0.01
-4
-3
-2
-1
10
10
10
S
qu
are
W
a
v
e P
u
lse D
u
ration (s)
10
1
Normalized Thermal Transient Impedance, Junction-to-Case
Note
•
The characteristics shown in the two graphs
– Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
– Normalized Transient Thermal Impedance Junction-to-Case (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board – FR4, size 1″ x 1″ x 0.062″, double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
S16-2192-Rev. A, 24-Oct-16
Document Number: 62896
6
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
Package Information
Vishay Siliconix
PowerPAK
®
1212-8W Case Outline
L
E2
E4
K
H
A2
W
8
7
1
2
3
4
1
2
3
4
Z
2
6
5
L1
E3
Back
s
ide view of
s
ingle pad
θ
θ
A1
Notes
1 Inch
will govern
2 Dimen
s
ion
s
exclu
s
ive of mold gate burr
s
3 Dimen
s
ion
s
exclu
s
ive of mold fla
s
h and
cutting burr
s
2
E1
E
Detail Z
MILLIMETERS
NOM.
1.04
INCHES
DIM.
MIN.
0.97
0
MAX.
1.12
0.05
0.13
0.41
0.33
3.40
3.15
2.24
MIN.
0.038
0
NOM.
0.041
MAX.
0.044
0.002
0.005
0.016
0.013
0.134
0.124
0.088
A
A1
A2
b
–
–
0
–
0
–
0.23
0.23
3.20
2.95
1.98
0.30
0.009
0.009
0.126
0.116
0.078
0.012
c
0.28
0.011
D
3.30
0.130
D1
D2
D4
D5
E
3.05
0.120
2.11
0.083
0.47 typ.
2.3 typ.
3.30
0.0185 typ.
0.090 typ.
0.130
3.20
2.95
1.47
1.75
3.40
3.15
1.73
1.98
0.126
0.116
0.058
0.069
0.134
0.124
0.068
0.078
E1
E2
E3
E4
e
3.05
0.120
1.60
0.063
1.85
0.073
0.34 typ.
0.65 BSC.
0.86 typ.
0.41
0.013 typ.
0.026 BSC
0.034 typ.
0.016
K
H
0.30
0.30
0.06
0°
0.51
0.56
0.20
12°
0.012
0.012
0.002
0°
0.020
0.022
0.008
12°
L
0.43
0.017
L1
0.13
0.005
–
–
W
M
0.15
0.25
0.36
0.006
0.010
0.014
0.125 typ.
0.005 typ.
ECN: C15-1530-Rev. B, 16-Nov-15
DWG: 6032
Revision: 16-Nov-15
Document Number: 64614
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
AN822
Vishay Siliconix
®
PowerPAK 1212
Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
The PowerPAK 1212-8 has a footprint area compara-
ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack-
ages are typically required solely for thermal consider-
ation, the PowerPAK 1212-8 is a good option.
with die on resistances around 1 m
Ω
and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable.
PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a deriva-
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
on the PowerPAK 1212-8 single in the index of this
document.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
2
area of about 0.3 to 0.5 in
of will yield little improve-
ment in thermal performance.
Figure 1.
PowerPAK 1212 Devices
Document Number 71681
03-Mar-06
1
AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in
of will yield little improve-
Ramp-Up Rate
+ 6
°
C /Second Maximum
2
T
e
mperature at 155
15
°
C
T
e
mperature Above 180
°
C
Maximum
T
e
mperature
Time at Maximum
T
e
mperature
Ramp-Down Rate
120 Seconds Maximum
ment in thermal performance.
70 – 180 Seconds
240 + 5/- 0
°
C
20 – 40 Seconds
REFLOW SOLDERING
+ 6
°
C/Second Maximum
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
Figure 2.
Solder Reflow Temperature Profile
10 s (max)
210 – 220 °C
3
°
C
/s (max)
4
°
C
/s (max)
1
8
3 °C
140 – 170 °C
50 s (max)
3° C/s (max)
60 s (min)
Reflo
w
Zone
Pre-Heating Zone
Maxim
u
m peak temperat
u
re at 240 °C is allo
w
ed.
Figure 3.
Solder Reflow Temperatures and Time Durations
2
Document Number 71681
03-Mar-06
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
SO-8
Single
20
TSSOP-8
TSOP-8
P
P
A
K 1212
P
P
A
K SO-8
Single Dual
1.8 5.5
Configuration
Dual
Single
Dual
Single
40
Dual
Single
Dual
40
52
83
90
2.4
5.5
Thermal Resiatance R
thJC
(C/W)
Po
w
erPAK 1212
49.
8
°C
Standard SO-
8
Standard TSSOP-
8
TSOP-6
8
5 °C
149 °C
125 °C
2.4 °C/
W
20 °C/
W
52 °C/
W
40 °C/
W
PC Board at 45 °C
Figure 4.
Temperature of Devices on a PC Board
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
Designers add additional copper, spreading copper, to
the junction-to-case thermal resistance, R
θ
jc, or the
the drain pad to aid in conducting heat from a device. It
junction to- foot thermal resistance, R
θ
jf. This parameter
is helpful to have some information about the thermal
is measured for the device mounted to an infinite heat
performance for a given area of spreading copper.
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
By minimizing the junction-to-foot thermal resistance, the
cations. The top layer was cut back to a smaller area and
MOSFET die temperature is very close to the tempera-
at each step junction-to-ambient thermal resistance
ture of the PC board. Consider four devices mounted on
measurements were taken. The results indicate that an
a PC board with a board temperature of 45 °C (Figure 4)
.
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
Power
P
A
K 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
er
P
A
K 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
P
A
K 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on r
whereas a rise
DS(ON)
of over 40 °C will cause an increase in r
as 20 %.
as high
DS(ON)
Document Number 71681
03-Mar-06
3
AN822
Vishay Siliconix
130
120
110
100
90
105
Spreading Copper (s
q
. in.)
Spreading Copper (s
q
. in.)
95
8
5
75
65
55
45
8
0
50
%
100
%
70
100
%
0
%
60
50
%
0
%
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6.
Spreading Copper – Junction-to-Ambient Performance
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5.
Spreading Copper – Si7401DN
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK
The PowerPAK 1212-8 combines small size with attrac-
1212-8 uses the same packaging technology and has
tive thermal characteristics. By minimizing the thermal
been shown to have the same level of thermal perfor-
rise above the board temperature, PowerPAK simplifies
mance while having a footprint that is more than 40 %
thermal design considerations, allows the device to run
smaller than the standard TSSOP-8.
cooler, keeps r
low, and permits the device to
DS(ON)
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
4
Document Number 71681
03-Mar-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM
P
A
DS FOR Power
P
A
K
®
1212-8 Single
0.152
(3.860)
0.039
0.068
0.010
(0.255)
(0.990)
(1.725)
0.016
(0.405)
0.026
(0.660)
0.025
0.030
(0.635)
(0.760)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72597
Revision: 21-Jan-08
7
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