Vishay-Intertech-VS-P421

VS-P400 Series  

Vishay Semiconductors  

Power Modules,  

Passivated Assembled Circuit Elements, 40 A  

FEATURES  

• Glass passivated junctions for greater reliability  

• Electrically isolated base plate  

• Available up to 1200 V

RRM

/V

DRM  

• High dynamic characteristics  

• Wide choice of circuit configurations  

• Simplified mechanical design and assembly  

• UL E78996 approved  

PACE-PAK (D-19)  

• Material

 

categorization: for definitions of compliance  

please see

PRIMARY CHARACTERISTICS  

DESCRIPTION  

I

O  

40 A  

The VS-P400 series of integrated power circuits consists of  

power thyristors and power diodes configured in a single  

package. With its isolating base plate, mechanical designs  

are greatly simplified giving advantages of cost reduction  

and reduced size.  

Type  

Modules – thyristor, standard  

PACE-PAK (D-19)  

Package  

Applications include power supplies, control circuits and  

battery chargers.  

MAJOR RATINGS AND CHARACTERISTICS  

SYMBOL  

CHARACTERISTICS  

VALUES  

40  

UNITS  

I

O  

80 °C  

50 Hz  

60 Hz  

50 Hz  

60 Hz  

A

385  

I

TSM

,



 

I

FSM  

A

400  

745  

I

2

t  

A

2

s  

680  

I

2



t  

7450  

A

2



s  

V

V

RRM  

V

ISOL  

T

J  

Range  

400 to 1200  

2500  

V

-40 to +125  

°C  

T

Stg  

ELECTRICAL SPECIFICATIONS  

VOLTAGE RATINGS  

V

RRM

/V

DRM

, MAXIMUM  

V

I

REPETITIVE PEAK REVERSE AND  

NON-REPETITIVE PEAK  

TYPE NUMBER  

AT T

J

MAXIMUM  

mA  

PEAK OFF-STATE VOLTAGE  

V

REVERSE VOLTAGE  

V

VS-P401, VS-P421, VS-P431  

VS-P402, VS-P422, VS-P432  

VS-P403, VS-P423, VS-P433  

VS-P404, VS-P424, VS-P434  

VS-P405, VS-P425, VS-P435  

400  

600  

500  

700  

800  

900  

10  

1000  

1200  

1100  

1300  

Revision: 27-Jul-2018  

Document Number: 93755  

1

For technical questions within your region:

,

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  

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A

T

VS-P400 Series  

Vishay Semiconductors  

ON-STATE CONDUCTION  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

Full bridge circuits  

VALUES  

40  

UNITS  

A

Maximum DC output current

  

at case temperature  

I

O  

80  

°C  

t = 10 ms  

t = 8.3 ms  

t = 10 ms  

t = 8.3 ms  

t = 10 ms  

t = 8.3 ms  

t = 10 ms  

t = 8.3 ms  

385  

400  

325  

340  

745  

680  

530  

480  

No voltage  

reapplied  

Maximum peak, one-cycle

  

non-repetitive on-state or

  

forward current  

I

TSM  

I

FSM  

,

A

100 % V

RRM  

reapplied  

Sinusoidal half wave,

  

initial T

J

= T

J

maximum  

No voltage  

reapplied  

Maximum I

2

t for fusing  

I

2

t  

A

2

s  

100 % V

RRM  

reapplied  

t = 0.1 ms to 10 ms, no voltage reapplied

  

I

2

t for time tx = I

2



t ·



tx  

Maximum I

2



t for fusing  

I

2



t  

7450  

A

2



s  

Low level value of threshold voltage  

High level value of threshold voltage  

Low level value of on-state slope resistance  

High level value of on-state slope resistance  

Maximum on-state voltage drop  

V

T(TO)1  

V

T(TO)2  

r

t1  

(16.7 % x



x I

T(AV)

< I <



x I

T(AV)

), T

J

= T

J

maximum  

(I >



x I

T(AV)

), T

J

= T

J

maximum  

0.83  

1.03  

9.61  

7.01  

1.4  

V

(16.7 % x



x I

T(AV)

< I <



x I

T(AV)

), T

J

= T

J

maximum  

(I >



x I

T(AV)

), T

J

= T

J

maximum  

m

  

r

t2  

V

TM  

V

FM  

I

TM

=



x I

T(AV)  

T

J

= 25 °C  

T

J

= 25 °C  

V

V

Maximum forward voltage drop  

I

FM

=



x I

F(AV)  

1.4  

Maximum non-repetitive rate of rise of

  

T

J

= 125 °C from 0.67 V

DRM

  

dI/dt  

200  

A/μs  

mA  

turned-on current  

I

TM

=



x I

T(AV)

, I

g

= 500 mA, t

r

< 0.5 μs, t

p

> 6 μs  

Maximum holding current  

Maximum latching current  

I

H  

I

L  

130  

250  

T

J

= 25 °C anode supply = 6 V, resistive load  

BLOCKING  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

VALUES  

UNITS  

Maximum critical rate of rise of

  

off-state voltage  

dV/dt  

T

J

= 125 °C, exponential to 0.67 V

DRM

gate open  

200  

V/μs  

Maximum peak reverse and off-state  

leakage current at V

RRM

, V

DRM  

I

RRM  

I

DRM  

,

T

J

= 125 °C, gate open circuit  

T

J

= 25 °C  

10  

mA  

μA  

V

Maximum peak reverse leakage current  

I

RRM  

100  

50 Hz, circuit to base, all terminals shorted,

  

T

J

= 25 °C, t = 1 s  

RMS isolation voltage  

V

ISOL  

2500  

TRIGGERING  

PARAMETER  

SYMBOL  

P

GM  

TEST CONDITIONS  

VALUES  

UNITS  

Maximum peak gate power  

Maximum average gate power  

Maximum peak gate current  

Maximum peak negative gate voltage  

8

2

W

P

G(AV)  

I

GM  

2

A

V

-V

GM  

10  

3

T

J

= – 40 °C  

T

J

= 25 °C  

Maximum gate voltage required to trigger  

Maximum gate current required to trigger  

V

GT  

2

V

T

J

= 125 °C  

T

J

= – 40 °C  

T

J

= 25 °C  

T

J

= 125 °C  

1

Anode supply =

  

6 V resistive load  

90  

60  

35  

0.2  

2

I

GT  

mA  

Maximum gate voltage that will not trigger  

Maximum gate current that will not trigger  

V

GD  

I

GD  

V

T

J

= 125 °C, rated V

DRM

applied  

mA  

Revision: 27-Jul-2018  

Document Number: 93755  

2

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,

,

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH

A

T

VS-P400 Series  

Vishay Semiconductors  

THERMAL AND MECHANICAL SPECIFICATIONS  

PARAMETER  

SYMBOL  

TEST CONDITIONS  

VALUES  

UNITS  

Maximum junction operating

  

and storage temperature range  

T

J

, T

Stg  

-40 to +125  

°C  

Maximum thermal resistance,

  

R

thJC  

R

thCS  

DC operation  

Mounting surface, smooth and greased  

1.05  

0.10  

junction to case per junction  

K/W  

Maximum thermal resistance,

  

case to heatsink  

Mounting torque, base to heatsink

(1)  

Approximate weight  

4

Nm  

g

58  

2.0  

oz.  

Case style  

PACE-PAK (D-19)  

Note  

(1)  

A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound  

120  

100  

80  

60  

40  

20  

0

120  

100  

80  

60  

40  

20  

0

+

–

~

180°  

(

s

ine)  

T

J

= 125 °C  

0

25  

50  

75  

100  

125  

0

5

10  

15  

20  

25  

30  

35  

40  

Maximum Allowa

b

le  

93755_01a  

Total Output Current (A)  

93755_01b  

Am

b

ient Temperature (°C)  

Fig. 1 – Current Ratings Nomogram (1 Module Per Heatsink)  

30  

40  

35  

DC  

180°  

120°  

90°  

60°  

30°  

25  

20  

15  

10  

5

180°  

120°  

90°  

60°  

30°  

30  

25  

RM

S

limit  

RM

S

limit  

20  

15  

Ø

Ø

10  

Conduction period  

Conduction angle  

T

J

= 125 °C  

Per junction  

T

J

= 125 °C  

Per junction  

5

0

0

0

5

10  

15  

20  

0

5

10  

15  

20  

25  

30  

35  

93755_02  

Average On-

S

tate Current (A)  

Fig. 2 – On-State Power Loss Characteristics  

93755_03  

Average On-

S

tate Current (A)  

Fig. 3 – On-State Power Loss Characteristics  

Revision: 27-Jul-2018  

Document Number: 93755  

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  

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A

T

VS-P400 Series  

Vishay Semiconductors  

130  

120  

110  

100  

90  

350  

325  

300  

275  

250  

225  

200  

175  

150  

At any rated load condition and with  

rated V

RRM

applied following

s

urge.  

Initial T

J

= 125 °C  

Fully turned-on  

at 60 Hz 0.0083

s  

at 50 Hz 0.0100

s  

180°  

(Rect.)  

180°  

(

S

ine)  

80  

Per junction  

Per module  

70  

0

5

10 15 20 25 30 35 40 45  

1

10  

100  

Num

b

er of Equal Amplitu

d

e Half  

93755_04  

Total Output Current (A)  

93755_06  

Cycle Current Pulses (N)  

Fig. 4 – Current Ratings Characteristics  

Fig. 6 – Maximum Non-Repetitive Surge Current  

1000  

100  

10  

400  

Maximum non-repetitive

s

urge current  

ver

s

u

s

pul

s

e train duration. Control of  

conduction may not be maintained.  

Initial T

J

= 125 °C  

T

J

= 25 °C  

350  

No voltage reapplied  

Rated V

RRM

reapplied  

T

J

= 125 °C  

300  

250  

200  

150  

Per junction  

Per junction  

1

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  

0.01  

0.1  

1

Instantaneous On-

S

tate Voltage (V)  

93755_05  

Pulse Train Duration (s)  

93755_07  

Fig. 7 – Maximum Non-Repetitive Surge Current  

Fig. 5 – On-State Voltage Drop Characteristics  

10  

S

teady

s

tate value  

R

(DC operation)  

1

0.1  

Per junction  

0.01  

0.0001  

0.001  

0.01  

0.1  

1

93755_08  

S

quare Wave Pulse Duration (s)  

Fig. 8 – Thermal Impedance Z

thJC

Characteristics  

Revision: 27-Jul-2018  

Document Number: 93755  

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A

T

VS-P400 Series  

Vishay Semiconductors  

100  

(1) P

G

M

= 10 W,

 

t

p

= 5 m

s  

(2) P

G

M

= 20 W,

 

t

p

= 25 m

s  

(3) P

G

M

= 50 W,

 

t

p

= 1 m

s  

(4) P

G

M

= 100 W,

 

t

p

= 500 μ

s  

Rectangular gate pul

s

e  

(a) Recommended load line for  

rated dI/dt: 10 V, 20

Ω

, t

r

≤ 1 μ

s  

(b) Recommended load line for  

rated dI/dt: 10 V, 65

Ω

, t

r

≤ 1 μ

s  

(a)  

10  

(b)  

1

(1)  

(2)  

(3)  

(4)  

V

G

D  

Fre

q

uency limited by P

G

(AV)  

I

G

D  

0.1  

0.001  

0.01  

0.1  

1

10  

100  

93755_09  

Instantaneous

G

ate Current (A)  

Fig. 9 – Gate Characteristics  

ORDERING INFORMATION TABLE  

Device code  

VS-  

P

4

0

2

K

W

1

2

3

4

5

6

7

1

2

3

–

–

–

Vi

s

hay

S

emiconductor

s

product  

Module type  

Current rating  

1 = 25 A DC (P100

s

erie

s

)  

4 = 40 A DC (P400

s

erie

s

)  

–

–

Circuit configuration  

4

5

0 =

s

ingle pha

s

e, hybrid bridge common cathode  

2 =

s

ingle pha

s

e, hybrid bridge doubler connection  

3 =

s

ingle pha

s

e, all

S

CR bridge  

Voltage code  

1 =

 

400 V  

2 =

 

600 V  

3 =

 

800 V  

4 = 1000 V  

5 = 1200 V  

6

7

–

–

K = optional voltage

s

uppre

ss

ion  

W = optional freewheeling diode  

Revision: 27-Jul-2018  

Document Number: 93755  

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  

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A

T

VS-P400 Series  

Vishay Semiconductors  

CIRCUIT CONFIGURATION  

CIRCUIT  

CONFIGURATION  

CODE  

CIRCUIT DESCRIPTION  

SCHEMATIC DIAGRAM  

TERMINAL POSITIONS  

G

1  

AC1  

AC2  

AC1

G

1  

AC2

G

2  

–

Single phase, hybrid bridge  

common cathode  

0

2

3

+

G

2  

(-)  

(+)  

G

1  

G

2  

AC2  

AC1  

AC1

G

1  

AC2

G

2  

–

Single phase, hybrid bridge  

doubler connection  

+

(-)  

(+)  

G

3  

G

1  

AC1  

AC2  

AC2

G

2  

G

1

G

4  

AC1

G

3  

–

Single phase, all SCR bridge  

+

G

4

G

2  

(-)  

(+)  

CODING

(1)  

WITH BOTH  

VOLTAGE SUPPRESSION  

AND FREEWHEELING  

DIODE  

CIRCUIT  

CONFIGURATION  

CODE  

WITH  

FREEWHEELING  

DIODE  

BASIC  

SERIES  

WITH VOLTAGE  

SUPPRESSION  

CIRCUIT DESCRIPTION  

Single phase, hybrid bridge  

common cathode  

0

P40.  

P40.K  

P40.W  

P40.KW  

Single phase, hybrid bridge  

doubler connection  

2

3

P42.  

P43.  

P42.K  

P43.K  

–

–

–

–

Single phase, all SCR bridge  

Note  

(1)  

To complete code refer to Voltage Ratings table, i.e.: for 600 V P40.W complete code is P402W  

LINKS TO RELATED DOCUMENTS  

Dimensions  

Revision: 27-Jul-2018  

Document Number: 93755  

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Outline Dimensions  

Vishay Semiconductors  

D-19 PACE-PAK  

DIMENSIONS

in millimeters (inches)  

0.9 x 45°  

(0.035 x 45°)  

Ø 1.65 (0.06)  

12.7 (0.50)

 

12.7 (0.50)  

4.6 (0.18)  

25 (0.98) MAX.  

15.5 (0.61)  

MAX.  

2.5 (0.10)  

MAX.  

63.5 (2.50)  

45 (1.77)  

Fast-on 6.35 x 0.8 (0.25 x 0.03)  

23.2 (0.91)  

32.5 (1.28) MAX.  

5.2 (0.20)  

33.8 (1.33)  

48.7 (1.91)  

Document Number: 95335  

Revision: 24-Jul-08  

For technical questions, contact:

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Disclaimer  

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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  

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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  

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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  

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liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  

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requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements  

about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product  

with the properties described in the product specification is suitable for use in a particular application. Parameters provided in  

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parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts.  

Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited  

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Revision: 01-Jan-2023  

Document Number: 91000  

1