WILLSEMI-Will-Semicon-WNMD2196A-14-TR
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WNMD2196A
WNMD2196A
Dual N-Channel, 12V, 19A, Power MOSFET
V
sss
(V)
Max R
(mΩ)
ss(on)
1.5@ V
GS
=4.5V
1.7@ V
GS
=3.8V
2.6@ V
GS
=3.1V
4.0@ V
GS
=2.5V
12
ESD Rating:2000V HBM
Gate1 (FET1) = 1
Source1 (FET1) = 2,3,4,5,6,7
Gate2 (FET2) = 8
Descriptions
The WNMD2196A is Dual N-Channel enhancement
MOS Field Effect Transistor and connecting the Drains
on the circuit board is not required because the Drains
of the MOSFET1 and the MOSFET2 are internally
connected. Uses advanced trench technology and
design to provide excellent R
SS(ON)
with low gate charge.
This device is designed for Lithium-Ion battery
protection circuit.
The WNMD2196A is available in
CSP-14L package. Standard Product WNMD2196A is
Pb-free and Halogen-free.
Source2 (FET2) = 9,10,11,12,13,14
CSP-14L (Top view)
S2
MOSFET2
G2
G1
MOSFET1
S1
Pin Configuration
Features
Trench Technology
Supper high density cell design
Excellent ON resistance for higher DC current
Extremely Low Threshold Voltage
Common-drain type
2196 = Device Code
ND = Special Code
Y =
Y
e
ar
Small package CSP-14L
W = Week
Marking
Applications
Order information
Device
Package
Shipping
Lithium-Ion battery protection circuit
WNMD2196A-14/TR
CSP-14L
3000/Reel&
T
a
pe
Will Semiconductor Ltd.
1
2021/12/21-Rev.1.0
WNMD2196A
Absolute Maximum ratings
Parameter
Symbol
V
SS
Maximum
12
Unit
Source -Source Voltage
Gate-Source Voltage
V
V
GS
±8
a
I
S
19
Continuous Source Current
Pulsed Source Current
c
T
A
=25°C
T
A
=25°C
b
I
S
48
A
I
SM
189
a
P
D
0.57
Maximum Power Dissipation
W
b
P
D
3.62
Operating Junction
T
e
mperature
Storage
T
emperature Range
T
J
-55 to 150
-55 to 150
°C
°C
T
STG
Thermal resistance ratings
Single Operation
Parameter
Symbol
Typical
146
Maximum
Unit
a
R
θJA
219
35
Junction-to-Ambient Thermal Resistance
°C/W
b
R
θJA
30
Note:
a. FR-4
board (38mm X 38mm X t1.6mm, 70um Copper) minimum pad covered with copper.
b. Ceramic
substrate (70 mm X 70 mm X t1.0 mm, 70um Copper) fully covered with copper.
c. Repetitive
rating, ~10us pulse width, duty cycle ~1%, keep initial T
J
=25°C, the maximum allowed junction temperature
of 150°C.
d. The
static characteristics are obtained using ~380us pulses, duty cycle ~1%.
Will Semiconductor Ltd.
2
2021/12/21-Rev.1.0
WNMD2196A
Electronics Characteristics
(T
A
=25
o
C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max Unit
OFF CHARACTERISTICS
Source to Source Voltage
V
SSS
V
GS
= 0
V
,
I
S
= 1mA
12
V
Zero Gate Voltage Drain Current
I
SSS
V
SS
=10
V
,
V
GS
= 0V
V
SS
= 0
V
,
V
GS
= ±8V
V
SS
= 0
V
,
V
GS
= ±5V
TEST CIRCUIT 1
TEST CIRCUIT 2
TEST CIRCUIT 2
1
uA
uA
uA
±10
±1
Gate Leakage Current
I
GSS
ON CHARACTERISTICS
Gate to Source Cut-off Voltage
V
GS
(th)
V
SS
= 10
V
,
I
S
= 1mA
TEST CIRCUIT 3
V
GS
= 4.5
V
,
I
S
= 9.8A
TEST CIRCUIT 4
0.5
0.7
0.9
1.1
1.4
1.5
1.7
2.6
4.0
V
1.2
V
GS
= 3.8
V
,
I
S
= 9.8A
TEST CIRCUIT 4
0.75
Source to Source On-state
Resistance
R
SS(on)
mΩ
V
GS
= 3.1
V
,
I
S
= 9.8A
TEST CIRCUIT 4
V
GS
= 2.5
V
,
I
S
= 9.8A
TEST CIRCUIT 4
0.8
0.9
1.45
1.95
BODY DIODE CHARACTERISTICS
Body Diode Forward Voltage
SWITCHING CHARACTERISTICS
Turn-On Delay Time
*
Rise Time
*
Turn-Off Delay Time
*
Fall Time
*
V
F(S-S)
V
GS
= 0
V
,
I
F
= 9.8A
TEST CIRCUIT 7
0.7
1.2
V
td(ON)
1.5
4.0
6.5
6.7
tr
V
GS
= 4.0
V
,
V
SS
=6.0
V
,
I
S
=9.8A,
us
TEST CIRCUIT 5
td(OFF)
tf
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
*
C
ISS
5989
1200
927
V
GS
= 0
V
, f =
1
kHz,
V
SS
= 10 V
Output Capacitance
*
C
OSS
C
RSS
pF
nC
Reverse Transfer Capacitance
*
T
o
tal Gate Charge
*
Q
G(TOT)
Q
G(TH)
Q
GS
62
6
Threshold Gate Charge
*
Gate-to-Source Charge
*
Gate-to-Drain Charge
*
V
G1S1
= 4.0
V
,
V
SS
= 6.0
V
,
I
S
=
9.8A
TEST CIRCUIT 6
14
21
Q
GD
Note:
* Guaranteed by design, not subject to production testing
Test Circuit
Will Semiconductor Ltd.
3
2021/12/21-Rev.1.0
WNMD2196A
FET1 and the FET2 are both measured.
T
e
st circuits are example of measuring the FET1 side
Test Circuit 2
Test Circuit 1
Vsss/Isss
I
GSS
S2
S2
G2
G2
A
V
s
s
G1
G1
A
When FET1 is measured,
Gate and Source of FET2
are short-circuited.
V
GS
S1
S1
Test Circuit 3
V
GS
(th)
Test Circuit 4
R
ss(on)
S2
S2
G2
G1
I
S
G2
When FET1 is
measured,Gate and
Source of FET2
A
are short-circuited.
V
V
s
s
G1
V
GS
V
GS
S1
S1
Test Circuit 6
Qg
Test Circuit 5
t
d(on)
,t
r
,t
d(off)
,t
f
S2
S2
When FET1 is
measured,Gate
and Source of
FET2 are short-
circuited.
A
RL
G2
G1
G2
G1
V
RL
Vs
S
Vs
S
PG
PG
S1
S1
Test Circuit 7
V
F(S-S)
S2
Is
G2
V
GS
=0V
V
G1
When FET1 is measured,
+4.5V is added to V
GS
of F
E
T2.
S1
Will Semiconductor Ltd.
4
2021/12/21-Rev.1.0
WNMD2196A
Typical Characteristics (
T
A
=25
o
C, unless otherwise noted
)
4
V
V
V
V
t
V
2
D
20
V
SS
=10V
18
16
14
12
10
8
V
GS
=4.5V
1
0.1
T=85
o
C
V
GS
=3.8V
T=125
o
C
T=25
o
C
T=-40
o
C
V
GS
=3.1V
6
V
GS
=2.5V
0.01
1E-3
4
2
0
0.00
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.01
0.02
0.03
0.04
0.05
V
GS
-Gate to Source Voltage(V)
V
SS
-Source-to-Source Voltage (V)
Output Characteristics
d
Transfer Characteristics
d
3.0
5
4
3
2
1
0
ID=9.8A
2.5
2.0
1.5
1.0
0.5
0.0
V
GS
=2.5V
V
GS
=3.1V
85
o
C
125
o
C
25
o
C
V
GS
=3.8V
V
GS
=4.5V
-40
o
C
2
1
2
3
4
5
6
7
8
9
0
1
3
4
5
6
7
8
I
SS
-Source to Source Current(A)
V
GS
-Gate to Source Voltage (V)
On-Resistance vs. Source Current
d
On-Resistance vs. Gate-to-Source Voltage
d
1.5
1.2
I
S
=1mA
I
S
=9.8A
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.1
V
SS
=10V
V
GS
=4.5V
1.0
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature
(
o
C
)
Temperature
(
o
C
)
On-Resistance vs. Junction Temperature
d
Will Semiconductor Ltd.
Threshold Voltage vs. Temperature
5
2021/12/21-Rev.1.0
WNMD2196A
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
10
1
V
GS
=0V
f=1KHz
125
o
C
C
iss
85
o
C
25
o
C
0.1
C
oss
C
rss
-40
o
C
0.01
0
1
2
3
4
5
6
7
8
9
10
1E-3
V
SS
-Source to Source Voltage(V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
SS
-Source to Source Voltage (V)
Capacitance
Body Diode Forward Voltage
d
1000
100
10
1000
100
10
T
J(Max)
=150
0
C
T
A
=25
0
C
100us
Limit by Rdson
1ms
10ms
T
J(MAX)
=150
o
C
100ms
1
T
A
=25
o
C
1s
1
DC
Single Pulse
0.1
0.01
10s
Mount on FR-4 board
(38mm X 38mm X t1.6mm, 70um copper)
minimum pad covered with copper
Mount on FR-4 board
(38mm X 38mm X t1.6mm, 70um copper)
minimum pad covered with copper
0.1
1E-4
1E-3
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
Pulse Width(s)
V
SS
-Source to Source Voltage(V)
Single Pulse power
Safe Operating Power
4.0
V
SS
=6V
I
S
=9.8A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
60
70
Gate Charge Characteristics (nC)
Gate Charge Characteristics
Will Semiconductor Ltd.
6
2021/12/21-Rev.1.0
WNMD2196A
In Descending Order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pluse
10
1
0.1
0.01
1E-3
1E-4
1E-5
single pulse
Mount on FR-4 board
(38mm X 38mm X t1.6mm, 70um copper)
minimum pad covered with copper
1E-5
1E-4
1E-3
0.01
0.1
1
10
100
1000
Square Wave Pulse Duration (s)
Transient thermal response (Junction-to-Ambient)
Will Semiconductor Ltd.
7
2021/12/21-Rev.1.0
WNMD2196A
PACKAGE OUTLINE DIMENSIONS
CSP-14L
Dimensions inMillimeters
Symbol
Min
Typ
0.095
3.00
Max
0.125
3.04
2.78
0.23
A
D
0.075
2.96
2.70
0.17
E
2.74
b
0.2
d
0.25
e
0.406
2.03
e 1
e 2
e 3
e 4
e 5
L
0.8375
0.8375
0.7625
0.7625
0.925
1.075
0.355
0.6625
0.7375
0.922
1.072
0.928
1.078
L1
H
H1
H2
Will Semiconductor Ltd.
8
2021/12/21-Rev.1.0
WNMD2196A
RECOMMENDED LAND P
A
T
TERN (Unit: mm)
Will Semiconductor Ltd.
9
2021/12/21-Rev.1.0
WNMD2196A
TAPE AND REEL INFORMATION
Reel Dimensions
Tape Dimensions
P1
Quadrant Assignments For PIN1 Orientation In Tape
Q1 Q2
Q3
Q1 Q2
Q3
Q4
Q4
User Direction of Feed
RD
W
Reel Dimension
7inch
8mm
2mm
Q1
13inch
12mm
4mm
Q2
Overall width of the carrier tape
Pitch between successive cavity centers
P1
8mm
Q3
Pin1 Pin1
Quadrant
Q4
Will Semiconductor Ltd.
10
2021/12/21-Rev.1.0
